1. Field of the Invention
This invention relates to complementary metal oxide semiconductor (CMOS) devices having polysilicon gate electrodes and interconnecting conductors of a single conductivity and single impurity type and, more particularly, to a process for fabricating such a CMOS device.
2. Description of the Prior Art
A CMOS device consists of an n-FET and a p-FET which are coupled so that the source or drain of one device is connected to the source or drain of the other device. In operation, one of the transistors will be functioning and the other will be off. When operating conditions within the circuit dictate that the functioning transistor turn off, the transistor which was previously off will begin to function due to the interconnection of sources and/or drains of the two transistors. Thus, very little power is required during the non-switching state for these transistors, thereby enabling reduced power consumption. Other advantageous features of a CMOS device include high speed and performance. Balanced against these is the complexity of the processing technology of CMOS devices, particularly in meeting the stringent requirements of high integration (or packing) density and high performance in very large scale integrated circuit applications.
In an attempt to meet the above requirements, conventional metal gate CMOS processing techniques have been replaced by silicon gate technology since this provides an area savings due to the better tolerances arising from the self-aligned nature of such gate structures, due to the ability to provide an additional layer of interconnect and due to the availability of buried contacts.
In one example of prior art silicon gate CMOS processes, U.S. application Ser. No. 218,891 by R. F. Pfeifer and M. L. Trudel (hereafter, Pfeifer et al.) entitled "Method for Fabrication of Improved Complementary Metal Oxide Semiconductor Devices" and assigned to the assignee of the present invention, discloses forming the desired pattern of gate electrode and interconnecting conductors on a semiconductor substrate such that each of the gate electrodes and conductors overlies a thin layer of gate oxide and is covered by a suitable oxidation and diffusion mask. The oxidation and diffusion mask, which consists of a dual layer of silicon dioxide and silicon nitride, serves as an oxidation mask and an implant/diffusion mask for the gate electrodes. The source and drain regions of the p-FET's and n-FET's are alternatively masked and formed by diffusing or implanting p-type and n-type impurities into the substrate. A layer of barrier oxide is then thermally grown on the semiconductor substrate to completely cover the source and drain regions, thereby protecting these regions from further doping during subsequent doping of the gate electrodes and conductors. Thereafter, the oxidation and diffusion mask which overlies each of the gate electrodes and conductors is selectively removed (while leaving the source and drain regions covered), thereby exposing the underlying gate electrodes and conductors. The exposed gate electrodes and conductors are then doped using a conventional doping technique.
Using this process Pfeifer et al. provide a CMOS device having polysilicon gates of a single conductivity and n-type impurities.
Because all of the gate electrodes and conductors have the same type of impurities, Pfeifer et al. avoid the need for metal bridges between (n.sup.+ and p.sup.+) polysilicon conductors, which would otherwise be required, thereby making more efficient use of chip area. Also, because all the gate electrodes are not subjected to p-type dopant (e.g., boron) the problem of dopant (particularly, boron) penetration from the gate electrode, through the thin oxide layer which separates the gate electrode from the underlying semiconductor substrate, and into the underlying substrate thereby changing the threshold voltage of the p-FET or producing a short between their source and drain regions is eliminated.
In implementing the Pfeifer et al. process, the oxidation of source and drain regions may consume some of the dopant in these regions. This may result in a higher source-to-drain interconnect resistance, thereby decreasing the device speed. Also, the process requires precise determination of the etch time for removal of the oxidation and diffusion mask to prevent accidental removal of the oxide mask over the source and drain regions. As will be appreciated, it is desirable to have a process which provides the above-described advantages of Pfeiffer et al. and also eliminates these concerns with oxidation and etch time.